Arrangement for parallel programming of in-system programmable IC logical devices
October 5, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMicroprocessor oriented configurable logic element Programmable sequence generator Integrated circuit packaging configuration for rapid customized design and unique test capability Configurable electrical circuit having configurable logic elements and configurable interconnects Programmable logic array having a changeable logic structure Structure and method for multiplexing pins for in-system programming Patent #: 5237218 InventorsAssigneeApplicationNo. 957311 filed on 10/05/1992US Classes:326/39, Array (e.g., PLA, PAL, PLD, etc.)327/407Converging with plural inputs and single outputExaminersPrimary: Hudspeth, DavidAttorney, Agent or FirmInternational ClassH03K 019/177AbstractA plurality of programmable logic devices are connected in parallel to a programming command generator. A device selector connects individual devices with the programming command generator, thereby permitting the individual devices to be programmed without routing the programming data through other devices. In an alternative embodiment, an identification code is used to place the individual device in a condition to receive programming data. Using the teachings of this invention, programming data may initially be entered into a plurality of devices, and then the data entered in all the devices may be used to program the devices simultaneously. This procedure requires less time than entering data and giving each device the execute command in sequence. | |
