Abstract

In an external memory interface circuit included in a signal processing circuit which is for processing an input signal by using an external memory, the external memory interface circuit carries out initialization of the external memory on reception of a clear signal. In the initialization, an end address detecting circuit detects an end address of an address signal generated by an address generator and produces an end address detection signal. A signal generating circuit continuously generates an enable signal, a write-in pulse signal, and an address increment pulse signal until the signal generating circuit receives the end address detection signal after reception of the clear signal. A reset signal generating circuit generates an address reset signal on reception of the enable signal. A write-in register successively produces zero data while the write-in register receives the enable signal to write the zero data in the external memory in synchronism with the write-in pulse signal. The address register produces address zero on reception of the address reset signal and increasing the address of the external memory one by one in response to the address increment pulse signal.