Patent ReferencesMethod and apparatus for generating a noiseless sliding block code for a (1,7) channel with rate 2/3 Method and apparatus for converting a digital data Method and apparatus for encoding and decoding an NRZI digital signal with low DC component and minimum low frequency components Parallel to serial converter with complementary bit insertion for disparity reduction Apparatus utilizing a four state encoder for encoding and decoding A sliding block (1,7) code High speed telecommunication system using a novel line code Patent #: 5200979 InventorApplicationNo. 016561 filed on 02/11/1993US Classes:341/58, To or from minimum d.c. level codes341/52, To or from particular bit symbol341/68To or from NRZ (nonreturn-to-zero) codesExaminersPrimary: Williams, Howard L.Attorney, Agent or FirmInternational ClassH03M 005/00Foreign Application Priority Data1992-05-21 JPAbstractA secondary modulation method which replaces any bit excluding the leading bit of consecutive five or more ones in an odd-numbered bit pattern of a train of RLL-modulated data, with a zero to provide a modulated bit pattern having no consecutive zeros. It is therefore possible to form marks of a given width on a disk without any mark edge shift, thus preventing the level of the waveform of a signal read from a disk from falling below the slice level at the position where the waveform of the read signal should show "1". This can ensure the proper data reproduction.Field of SearchTo or from particular bit symbolSubstituting specified bit combinations for other prescribed bit combinations To or from minimum d.c. level codes To or from run length limited codes To or from NRZ (nonreturn-to-zero) codes Return-to-zero to or from NRZ (nonreturn-to-zero) codes To or from bi-phase level code (e.g., split phase code, Manchester code) To or from bi-phase space or mark codes (e.g., double frequency code, FM code) To or from delay modulation code (e.g., Miller code, three frequency code, MFM code) | |