Method for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability
Patent 5326428 Issued on July 5, 1994. Estimated Expiration Date: 
September 3, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 3, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesIntegrated test and assembly device Solid state multiprobe testing apparatus Method of manufacturing probing head for testing equipment of semi-conductor large scale integrated circuits Patent #: 4952272 InventorsAssigneeApplicationNo. 716394 filed on 09/03/1993US Classes:324/724, Using a probe type structure205/123, Product is semiconductor or includes semiconductor216/11, FORMING OR TREATING AN ARTICLE WHOSE FINAL CONFIGURATION HAS A PROJECTION324/500, FAULT DETECTING IN ELECTRIC CIRCUITS AND OF ELECTRIC COMPONENTS324/754, With probe elements438/17, Electrical characteristic sensed438/978FORMING TAPERED EDGES ON SUBSTRATE OR ADJACENT LAYERSExaminersPrimary: Powell, William A.Attorney, Agent or FirmInternational ClassesH01L 021/306B44C 001/22 C03C 015/00 C03C 025/06 AbstractA method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate. |
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