Patent ReferencesParallel command-status interface through multiplexed serial link Data processing system with a plurality of processors Microprocessor timing emulator having a "Wait" state Watchdog timer having a reset detection circuit Method and apparatus for testing a multi-processor system Resetting system Microcomputer system with watchdog timer System for reducing processor power consumption by stopping processor clock supply if a desired event does not occur Digital data processor with fault-tolerant peripheral interface Multiple event timer circuit InventorsApplicationNo. 146473 filed on 11/01/1993US Classes:714/55, Timing error (e.g., watchdog timer time-out)713/502Counting, scheduling, or event timingExaminersPrimary: Beausoliel, Robert W. Jr.Assistant: Chung, Phung M. International ClassG05F 011/34Foreign Application Priority Data1990-02-26 JPAbstractA wait control device according to the present invention instructs a central processing unit (CPU) to wait for the start of its operation until the device receives a process completion signal from a memory unit or an I/O unit, and comprises setting means for setting the time of said CPU to wait for the start of its operation in the memory unit or the I/O unit accessed by the CPU, judgement means for judging system operation to be time out error when no process completion signal is presented during said time of the CPU, and selector means for selecting whether it passes a signal concerning the judgement of the time out error or successively waits for said processing completion signal. | |