Time delay control for serial digital video interface audio receiver buffer
July 1, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod and apparatus for recording digitally coded television signals Apparatus for recording video and audio signals High-speed, asynchronous, No-Fall-Through, first-in-first out memory with high data integrity First-in first-out buffer memory with improved status flags Method of, and apparatus for, facilitating sychronization of recorded audio and video information First-in, first-out (FIFO) memory with variable commit point Patent #: 5016221 InventorAssigneeApplicationNo. 907426 filed on 07/01/1992US Classes:360/8, RECORDING FOR CHANGING DURATION, FREQUENCY OR REDUNDANT CONTENT OF AN ANALOG SIGNAL365/221, Serial read/write386/98Multiplexing or demultiplexingExaminersPrimary: Westin, Edward P.Assistant: Santamauro, Jon Attorney, Agent or FirmForeign Patent References
International ClassesG11B 005/00G11B 005/02 AbstractAn audio receiver FIFO memory buffer in the serial digital video interface allows improved timing synchronization between video and audio information. Furthermore, it eliminates unpleasant sound effects when multiple data samples are skipped or repeated in series. This FIFO receiver buffer receives data at an input write-data rate filling up the memory storage cells therein. An output read-data signal clocks the data out of the memory storage cells. The FIFO's fullness is monitored and maintained, in response to an external signal, to within a specified range delimited by an upper and a lower threshold. If the FIFO buffer fullness is below the range's lower threshold, then the FIFO's read address pointer is held so that the immediately preceding read out data element is read out again, but only once. On the other hand, the FIFO buffer fullness is over the range's upper limit, then the FIFO's write address pointer is held so that the immediately preceding written in data element is written over, but only once.Other References
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