U.S. patents available from 1976 to present.
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High frequency JFET

Patent 5321283 Issued on June 14, 1994. Estimated Expiration Date: Icon_subject July 30, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Process for monolithic integration of logic, control, and high voltage interface circuitry
Patent #: 4325180
Issued on: 04/20/1982
Inventor: Curran

ISFET sensor and method of manufacture
Patent #: 4505799
Issued on: 03/19/1985
Inventor: Baxter

Multi-drain enhancement JFET logic (SITL) with complementary MOSFET load
Patent #: 4700213
Issued on: 10/13/1987
Inventor: Nishizawa ,   et al.

Implantation of ions into an insulating layer to increase planar pn junction breakdown voltage
Patent #: 4827324
Issued on: 05/02/1989
Inventor: Blanchard

Device for detecting magnetism
Patent #: 5005064
Issued on: 04/02/1991
Inventor: Yoshino, et al.

High power MOSFET and integrated control circuit therefor for high-side switch application Patent #: 5023678
Issued on: 06/11/1991
Inventor: Kinzer

Inventors

Application

No. 737950 filed on 07/30/1991

US Classes:

257/256, Junction field effect transistor (unipolar transistor)257/487, WITH MEANS TO INCREASE BREAKDOWN VOLTAGE THRESHOLD257/490, Combined with floating pn junction guard region257/491, In integrated circuit257/651, Details of insulating layer electrical charge (e.g., negative insulator layer charge)257/E21.248, By ion implantation (EPO)257/E21.446, With PN homojunction gate (EPO)257/E29.013, With supplementary region doped oppositely to or in rectifying contact with semiconductor containing or contacting region(e.g., guard rings with PN or Schottky junction) (EPO)257/E29.015, With insulating layer characterized by dielectric or electrostatic property (e.g., including fixed charge or semi-insulating surface layer) (EPO)257/E29.059, Gate region of field-effect devices with PN junction gate (EPO)257/E29.313Vertical transistors (EPO)

Examiners

Primary: Hille, Rolf
Assistant: Fahmy, Wael

Attorney, Agent or Firm

International Classes

H01L 029/80
H01L 023/58
H01L 031/112

Abstract

The junction field effect transistors (JFETs) of this invention have improved breakdown voltage capability, reduced on-resistance and improved overdrive capability. The JFET on-resistance is decreased by ion-implanting an insulating layer covering a layer that contains the source and gate regions of the unipolar transistor. The charge of the implanted ions is the same as the charge polarity of the gate regions. To improve the overdrive capability of a JFET a region of conductivity opposite to the conductivity of the gate region is formed in the gate region of the transistor. This region of opposite conductivity creates another junction within the gate region i.e., the junction between the region of opposite conductivity and the gate region, and the junction between the gate region and the layer containing the gate region. The second junction in the gate region of this invention prevents the gate-to-source junction from becoming forward biased until higher gate voltages are applied and thereby provides increased overdrive capability in comparison to prior art JFETs. A new method is used to form a guard ring surrounding the active area of a JFET. The JFET formed using this method has a guard ring of a second conductivity type extending a first distance D1 into a layer having a first conductivity type and a gate region of the second conductivity type extending a second distance D2 into the layer. The method of this invention allows selection of the first and second distances D1, D2 to optimize the breakdown voltage and performance of the JFET of this invention.

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