Noise cancelling circuit
Input circuit having improved noise immunity
Integrated circuit comprising logic circuits and at least one push-pull stage
Output buffer having capacitive drive shunt for reduced noise
CMOS output driver with transition time control circuit Patent #: 5120992
ApplicationNo. 980877 filed on 11/24/1992
US Classes:326/21, SIGNAL SENSITIVITY OR TRANSMISSION INTEGRITY326/62, INTERFACE (E.G., CURRENT DRIVE, LEVEL SHIFT, ETC.)327/108, Current driver327/170Slope control of leading or trailing edge of rectangular (e.g., clock, etc.) or pulse waveform
ExaminersPrimary: Westin, Edward P.
Assistant: Driscoll, Benjamin D.
Attorney, Agent or Firm
Foreign Patent References
International ClassesH03K 019/07
Foreign Application Priority Data1992-05-14 JP
AbstractFirst and second capacitor circuits responsive to a potential applied to an input node for instantaneously supplying a voltage derived by capacitance division to control electrodes of first and second output MOS transistors which drive an output node. When the output node reaches a predetermined potential level, the control electrode node of the first output transistor or the control electrode node of the second output transistor is driven to ground potential or power supply potential by the MOS transistor responding to a delay signal of an input signal. A smaller buffer circuit which has improved output response and reduced through current is described. The output signal transitioning speed can also be easily altered.