Patent ReferencesThree level memory hierarchy using write and share flags Second level cache replacement method and apparatus Virtually addressed cache Dual cache for independent prefetch and execution units Prioritized secondary use of a cache with simultaneous access Cache memory consistency control with explicit software instructions Interleaved set-associative memory Hierarchical cache memory system and method Apparatus and method for prefetching subblocks from a low speed memory to a high speed memory of a memory hierarchy depending upon state of replacing bit in the low speed memory Multiprocessor coherent cache system including two level shared cache with separately allocated processor storage locations and inter-level duplicate entry replacement InventorsAssigneeApplicationNo. 059715 filed on 05/10/1993US Classes:711/3, Addressing cache memories711/122, Hierarchical caches711/207Directory tables (e.g., DLAT, TLB)ExaminersPrimary: Lall, Parshotam S.Assistant: Lim, Krisna Attorney, Agent or FirmInternational ClassG06F 012/08AbstractA two-level cache memory system for use in a computer system including two primary cache memories, one for storing instructions and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a "miss" is encountered in both the primary and secondary caches does the system processor access the main memory.Other References
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