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Two-level cache memory system

Patent 5307477 Issued on April 26, 1994. Estimated Expiration Date: Icon_subject May 10, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Three level memory hierarchy using write and share flags
Patent #: 4442487
Issued on: 04/10/1984
Inventor: Fletcher ,   et al.

Second level cache replacement method and apparatus
Patent #: 4464712
Issued on: 08/07/1984
Inventor: Fletcher

Virtually addressed cache
Patent #: 4612612
Issued on: 09/16/1986
Inventor: Woffinden ,   et al.

Dual cache for independent prefetch and execution units
Patent #: 4701844
Issued on: 10/20/1987
Inventor: Thompson ,   et al.

Prioritized secondary use of a cache with simultaneous access
Patent #: 4707784
Issued on: 11/17/1987
Inventor: Ryan ,   et al.

Cache memory consistency control with explicit software instructions
Patent #: 4713755
Issued on: 12/15/1987
Inventor: Worley, Jr. ,   et al.

Interleaved set-associative memory
Patent #: 4736293
Issued on: 04/05/1988
Inventor: Patrick

Hierarchical cache memory system and method
Patent #: 4755930
Issued on: 07/05/1988
Inventor: Wilson, Jr. ,   et al.

Apparatus and method for prefetching subblocks from a low speed memory to a high speed memory of a memory hierarchy depending upon state of replacing bit in the low speed memory
Patent #: 4774654
Issued on: 09/27/1988
Inventor: Pomerene ,   et al.

Multiprocessor coherent cache system including two level shared cache with separately allocated processor storage locations and inter-level duplicate entry replacement
Patent #: 4785395
Issued on: 11/15/1988
Inventor: Keeley

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Inventors

Assignee

Application

No. 059715 filed on 05/10/1993

US Classes:

711/3, Addressing cache memories711/122, Hierarchical caches711/207Directory tables (e.g., DLAT, TLB)

Examiners

Primary: Lall, Parshotam S.
Assistant: Lim, Krisna

Attorney, Agent or Firm

International Class

G06F 012/08

Abstract

A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instructions and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a "miss" is encountered in both the primary and secondary caches does the system processor access the main memory.

Other References

  • Baskett et al., "The 4D-MP Graphics Superworkstation"; 33rd IEEE Computer Society International Conference; Spring 1988, pp. 468-471
  • Stone; "High-Performance Computer Architecture: Cache memory"; Addition-Wesley; pp. 29-69; 1987
  • Taylor et al; "An ECL RISC microprocessor designed for two level cache"; 35th IEEE Computer Society International Conference; Spring 1990, pp. 228-23
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