Microcircuit package and sealing method
Method of manufacturing a multichip package with increased adhesive strength
Process for manufacturing a metal pin grid array package
Plastic pin grid array package
Semiconductor device and production method thereof
Method of manufacturing a high lead count circuit board Patent #: 5206188
ApplicationNo. 015510 filed on 02/09/1993
US Classes:29/832, Assembling to base an electrical component, e.g., capacitor, etc.257/E23.172, Assembly of plurality of insulating substrates (EPO)257/E23.173, Multilayer substrates (EPO)257/E23.174, Conductive vias through substrate with or without pins, e.g., buried coaxial conductors (EPO)257/E23.178, Chips being integrally enclosed by interconnect and support structures (EPO)257/E25.012, Devices being arranged next to each other (EPO)438/118, Including adhesive bonding step438/119, Electrically conductive adhesive438/126And encapsulating
ExaminersPrimary: Hearn, Brian E.
Assistant: Picardat, Kevin M.
Attorney, Agent or Firm
International ClassH01L 021/60
AbstractA multi-chip integrated circuit module includes a supporting layer of laminate material over which a high-density interconnect structure is formed. The laminate layer includes a first upper laminate layer (10) having a hole (14) disposed therein for receiving an integrated circuit chip die (56). A lower core laminate layer (16) having a conductive layer (18) and conductive layer (20) disposed on opposite sides thereof is laminated to the lower surface of the layer (10). Plated-through holes (36), (38) and (40) are formed through the two layers (10) and (16) to connect the conductive layer (20) with a conductive layer (12) on the upper surface of the layer (10). A high-density interconnect layer includes two laminate layers (126) and (138), each having vias formed therethrough and via interconnect structures disposed on the surfaces thereof. The via interconnect structures in the layer (126) allow for connections from the die (56) to the conductive layer (12). The via interconnect structures formed in the layer (138) allow interconnection from the upper surface of layer (138) to via interconnects formed in the layer (126). An I/O connector is interfaced with select ones of the plated-through holes with pins (162) and (164). This allows an interface from the module to an operating system through pins (166).