Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of data sets
April 5, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod and apparatus for controlling software configurations in data processing systems Dynamic configuration for added devices Reconfigurable memory system Data processing system and method having an improved arithmetic unit Dynamically configurable portable computer system Apparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respectively define plurality of predetermined counters Inter-configuration changing controller based upon the connection and configuration information among plurality of clusters and the global storage Method for converting a programmable logic controller hardware configuration and corresponding control program for use on a first programmable logic controller to use on a second programmable logic controller Patent #: 5142469 InventorAssigneeApplicationNo. 647557 filed on 01/29/1991US Classes:712/32, Microprocessor or multichip or multimodule processor having sequential program control712/37Programmable (e.g., EPROM)ExaminersPrimary: Lall, Parshotam S.Assistant: Lim, Krisna Attorney, Agent or FirmInternational ClassG06F 013/00AbstractA reconfigurable sequential processor includes a data bank for storing data to be processed; a programmable logic block address generator for addressing data in the data bank; a programmable logic block arithmetic unit responsive to the data bank for processing the data addressed by the programmable logic block address generator; an address generator hardware configuration file having a plurality of configuration files for configuring the programmable logic block address generator in one of a plurality of addressing configurations in response to an address operational code; an arithmetic hardware configuration file having a plurality of configuration files for configuring the programmable logic block arithmetic unit in one of a plurality of processing configurations in response to an arithmetic operational code; and for delivering a series of operational codes to each configuration file for enabling the programmable logic block address generator and the programmable logic block arithmetic unit to be configured to perform sequentially a corresponding series of arithmetic logic operations on the data in the data bank. | |
