Cache coherency protocol for multi processor computer system
Patent 5297269 Issued on March 22, 1994. Estimated Expiration Date: 
May 24, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
May 24, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3422401 3510844 3735360 3771137 Storage interface unit Backing store access coordination in a multi-processor system Multi-configurable cache store system Multi-processor task dispatching apparatus Cache storage line shareability control for a multiprocessor system Apparatus for cache clearing Inventors
AssigneeApplicationNo. 066597 filed on 05/24/1993US Classes:711/145, Access control bit711/130, Shared cache711/163Access limitingExaminersPrimary: Chan, Eddie P.Attorney, Agent or FirmInternational ClassG06F 012/00AbstractA cache coherency protocol for a multi-processor system which provides for read/write, read-only and transitional data states and for an indication of these states to be stored in a memory directory in main memory. The transitional data state occurs when a processor requests from main memory a data block in another processor's cache and the request is pending completion. All subsequent read requests for the data block during the pendency of the first request are inhibited until completion of the first request. Also provided in the memory directory for each data block is a field for identifying the processor which owns the data block in question. Data block ownership information is used to determine where requested owned data is located.Other References
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