U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Circuit arrangement capable of centralizing control of a switching network

Patent 5293489 Issued on March 8, 1994. Estimated Expiration Date: Icon_subject May 13, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3428946

3781819

3916380

Digital multifrequency signalling receiver
Patent #: 4245325
Issued on: 01/13/1981
Inventor: Kikuchi ,   et al.

Array processor architecture connection network
Patent #: 4365292
Issued on: 12/21/1982
Inventor: Barnes ,   et al.

Device for switching digital data
Patent #: 4365328
Issued on: 12/21/1982
Inventor: Merriaux ,   et al.

Process for switching time-multiplexed signals transmitted on a carrier, including in particular an optical carrier, and a device embodying this process
Patent #: 4397016
Issued on: 08/02/1983
Inventor: Broussaud

Telecommunications switching network using digital switching modules
Patent #: 4425640
Issued on: 01/10/1984
Inventor: Philip ,   et al.

Shared memory computer method and apparatus
Patent #: 4484262
Issued on: 11/20/1984
Inventor: Sullivan ,   et al.

End-to-end information memory arrangement in a line controller
Patent #: 4488288
Issued on: 12/11/1984
Inventor: Turner

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Inventors

Assignee

Application

No. 060719 filed on 05/13/1993

US Classes:

710/317, Crossbar709/244Centralized controlling

Examiners

Primary: Harrell, Robert B.

Attorney, Agent or Firm

Foreign Patent References

  • 56-61892 JP. 05/13/1981
  • 57-43256 JP. 03/13/1982
  • 59-206960 JP. 11/13/1984

International Class

G06F 013/00

Foreign Application Priority Data

1985-01-24 JP

Abstract

In a circuit arrangement for use in accessing selected address numbered with a preselected distance left between two adjacent ones of the selected addresses, a control circuit centralizes control operation of a switching network with reference to a reference one of the selected addresses and the preselected distance to make the switching network form internal paths between input and output port sets of the switching network. Alternatively, when ports of a selected one of the input and output port sets are accessed at a predetermined port interval, the control circuit controls the switching network with reference to the predetermined port interval and a reference port selected from the selected port set. A leading port of the other set is determined to be connected to the reference port. A rearranging circuit may be connected to one of the input and output port sets to rearrange an order of the ports of the one port set in consideration of the port distance. The reference and leading ports may be varied in a time division fashion when a conflict of internal paths otherwise occurs in relation to the port distance.

Other References

  • Lawrie, D. H. "Access and alignment of data in an array processor", IEEE Transactions on Computer, vol. C-24, No. 12, Dec. 1975, pp. 1145-115
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