SOT CMOS device having differentially doped body extension for providing improved backside leakage channel stop
March 23, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesEdgeless transistor SOS Mosfet with thinned channel contact region SOS MOSFET With self-aligned channel contact Semiconductor device having a silicon on insulator structure Radiation hardened CMOS on SOI or SOS devices SOI layout for low resistance gate Thin-film SOI-MOSFET with a body region Extended body contact for semiconductor over insulator transistor Patent #: 5160989 InventorsAssigneeApplicationNo. 855834 filed on 03/23/1992US Classes:257/349, With means (e.g., a buried channel stop layer) to prevent leakage current along the interface of the semiconductor layer and the insulating substrate257/66, Field effect device in non-single crystal, or recrystallized, Semiconductor material257/347, Single crystal semiconductor layer on insulating substrate (SOI)257/655, WITH SPECIFIED IMPURITY CONCENTRATION GRADIENT257/E27.062, Complementary MIS (EPO)257/E27.111Substrate comprising other than a semiconductor material, e.g. insulating substrate or layered substrate Including a non-semiconductor layer (EPO)ExaminersPrimary: Hille, RolfAssistant: Loke, Steven Attorney, Agent or FirmForeign Patent References
International ClassesH01L 027/01H01L 027/12 H01L 029/04 H01L 029/36 AbstractAn SOI/SOS thin film MOS mesa architecture has its body/channel region extended beyond the source and drain regions and the impurity concentration is increased at an end portion of the extended body region, so as to provide a channel stop region that is effective to functionally interrupt a current leakage path or `parasitic` N-channel that may be induced along sidewall surface of the P-type material of the body/channel region. In addition, in order to inhibit radiation-induced leakage along a backside interface of the extended body region abutting an underlying dielectric substrate, a portion of the extended body region between the channel stop region and the body/channel region has an impurity concentration profile that is increased at the interface of the extended body region with the underlying dielectric substrate.Field of SearchField effect device in non-single crystal, or recrystallized, Semiconductor materialSingle crystal semiconductor layer on insulating substrate (SOI) Depletion mode field effect transistor With means (e.g., a buried channel stop layer) to prevent leakage current along the interface of the semiconductor layer and the insulating substrate Substrate is single crystal insulator (e.g., sapphire or spinel) Single crystal islands of semiconductor layer containing only one active device Including means to eliminate island edge effects (e.g., insulating filling between islands, or ions in island edges) BRIDGE RECTIFIER MODULE WITH SPECIFIED IMPURITY CONCENTRATION GRADIENT Stepped profile | |
