Method of fabricating semiconductor device
Method of fabricating a trench structure
Semiconductor processing method for forming substrate isolation trenches
Method of forming an integrated circuit capacitor dielectric and a capacitor formed thereby Patent #: 5250456
ApplicationNo. 071752 filed on 06/09/1993
US Classes:438/296, Dielectric isolation formed by grooving and refilling with dielectric material257/E21.546, Using trench refilling with dielectric materials (EPO)257/E21.628, Isolation region manufacturing related aspects, e.g., to avoid interaction of isolation region with adjacent structure (EPO)257/E21.648, Capacitor stacked over transfer transis tor (EPO)438/305Plural doping steps
ExaminersPrimary: Hearn, Brian E.
Assistant: Chaudhari, Chandra
Attorney, Agent or Firm
International ClassH01L 021/304
AbstractA semiconductor processing device isolation method includes: a) providing non-LOCOS insulating device isolation blocks by trench and refill technique on a substrate to define recessed moat volume therebetween; b) providing gate dielectric within the moat volume; c) providing a layer of electrically conductive material over the substrate and gate dielectric to a thickness sufficient to completely fill the moat volume between adjacent isolation blocks; d) chemical-mechanical polishing the layer of electrically conductive material to provide a planarized upper electrically conductive material surface; e) photopatterning and etching the layer of electrically conductive material to provide an electrically conductive runner which overlies a plurality of the isolation blocks and to selectively remove the electrically conductive material from within selected regions of moat volume to define field effect transistor gates within the moat volume; and f) providing conductivity enhancing impurity through the selected regions of moat volume into the substrate to define source/drain regions adjacent the field effect transistor gates. The invention also includes an array of memory integrated circuitry.