Method and apparatus for generating a noiseless sliding block code for a (1,7) channel with rate 2/3
Apparatus for encoding unconstrained data onto a (1,7) format with rate 2/3
Method and apparatus for processing sample values in a coded signal processing channel Patent #: 4945538
ApplicationNo. 526878 filed on 05/22/1990
US Classes:714/818, Missing-bit/drop-out detection341/58, To or from minimum d.c. level codes358/1.9, Attribute control714/786, Forward error correction by tree code (e.g., convolutional)714/798, Error detection for synchronization control714/811Forbidden combination or improper condition
ExaminersPrimary: Beausoliel, Robert
Assistant: Lo, Allen M.
Attorney, Agent or Firm
International ClassG06F 011/10
AbstractA signal processing channel and method are described for processing digital sample values corresponding to an incoming analog signal representative of coded binary data. An eight-sample look-ahead algorithm is used to precompute the values of functional expressions for a baseline check and for a peak-position check. These precomputed values are compared against appropriate thresholds to provide respective binary decision outputs which, with state values corresponding to the current state, are used to determine state values for the next state, which become the current state values for the next iteration of the clock cycle. During each of a series of successive clock cycles, one successive bit of coded binary data corresponding to said current sample value is decoded, and at the next clock cycle, the computed next state becomes the new current state. Sensitivity to missing or extra-bit errors is minimized and full advantage of a (1,7) run-length-limited code constraint is achieved. A phase check is not necessary.