U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Network rearrangement method and system

Patent 5287491 Issued on February 15, 1994. Estimated Expiration Date: Icon_subject February 15, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Dual rail dilated switching networks
Patent #: 5018129
Issued on: 05/21/1991
Inventor: Netravali, et al.

Self-routing switching system having dual self-routing switch module network structure Patent #: 5072440
Issued on: 12/10/1991
Inventor: Isono, et al.

Inventor

Application

No. 335916 filed on 04/10/1989

US Classes:

714/4, Of network340/2.23, Alternate routing370/217Bypass an inoperative switch or inoperative element of a switching system

Examiners

Primary: Baker, Stephen M.

Attorney, Agent or Firm

International Classes

G06F 011/20
G06F 013/36

Abstract

A system and method for a fault-tolerant system for parallel networks which interconnect processors and the first of the parallel networks distributed in an Omega configuration and the second of the parallel networks distributed in a reversed Omega configuration.

Other References

  • Yang, S. et al., "Graceful Degradation of Fault-Tolerant Multistage Interconnection Networks", Proceedings of the 1987 International Conf. on Parallel Processing, pp. 121-123
  • D. Lawrie, "Access and Alignment of Data in an Array Processor", IEEE Trans. on Computers, vol. C-24, No. 12, Dec. 1975, pp. 1145-1155
  • K. Padmanabhan et al., "A Class of Redundant Path Multistage Interconnection Network", IEEE Trans. on Computers, vol. C-32, No. 12, Dec. 1983, pp. 1099-1108
  • Wu C., et al., "The Reverse-Exchange Interconnection Network", IEEE Trans. on Computers, vol. C-29, No. 9, Sept. 1980, pp. 801-811
  • Moore, M., et al., "Bi-directional Networks for Large Parallel Processors", Computer Architecture News, vol. 15, No. 3, Jun. 1987, pp. 3-5
  • Castan, M., et al., "MaRS:A parallel graph reduction multiprocessor", Computer Architecture News, vol. 16, No. 3, Jun. 1988, pp. 17-24
  • Contessa, A., "An approach to fault tolerance and error recovery in a parallel graph reduction machine:MaRS-a case study", Computer Architecture News, vol. 16, No. 3, Jun. 1988, pp. 25-32
  • H. J. Siegel, W. T. -Y. Hsu, M. Jeng, "An Introduction to the Multistage Cube family of Interconnection Networks," Journal of Supercomputing, 1, 13-42(1987)
  • C. -L. Wu and T. -Y. Feng, "On A Class of Multistage Interconnection Networks," IEEE Transactions on computers, vol. C-29, No. 8, pp. 694-702, Aug. 198
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