Patent ReferencesBackup fault tolerant computer system Programmable sequence controller Redundant device control unit Reconfigurable dual processor system Patent #: 4823256 InventorAssigneeApplicationNo. 710333 filed on 06/05/1991US Classes:370/221, Bypass an inoperative station340/825.01, Spare channel700/2, Plural processors700/82Backup/standbyExaminersPrimary: Peng, John K.Assistant: Gray, Robert International ClassH04B 003/38Foreign Application Priority Data1990-06-05 JPAbstractAn electronic message transmission system including at least one transmission apparatus of the electronic message and a plurality of message receivers of the same wherein the electronic message is transmitted according to a predetermined transmission path connecting message receivers. A transmission state of the electronic message is memorized and up-dated in a memory and thereby, an addresser of the electronic message is able to know the state of the message transmission by referring to the contents of the memory. In another message transmission system, deputy confirmors are registered together with confirmors in respective message receivers and each deputy confirmor processes the transmitted message in place of the relevant confirmor if the confirmor is absent.Field of SearchSpare channel | |