Did You Know...
...that the Eveready Battery began as an invention called the "electric flowerpot," which was a tube with a battery and light bulb inside? The idea was to fasten this gizmo to the side of a flowerpot so it would illuminate the flowers from the bottom. The idea died on the vine and the businessman who licensed the flower pot, Conrad Huber, was left with a pile of useless tubes -- until he found a way to market them as batteries to light the world!
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US Patent 5285119 - Semiconductor integrated tri-state circuitry with test means
US Patent Issued on February 8, 1994
Estimated Patent Expiration Date:
April 13, 2012Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Estimated Patent Expiration Date:
April 13, 2012Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.AbstractA plurality of tristate circuits (TSG1, TSG2, TSG3) each include an input circuit (NAND1, NOR1; NAND2, NOR2; NAN3, NOR3) for receiving first and second control signals ($c;goe1*, in1; $c;goe2*, in2; $c;goe3*, in3) and a tristate output circuit (Q1p, Q1n; Q2p, Q2n; Q3n). The input circuits further receiving a test signal (TEST*). The tristate circuits each include a tristate output (OT1; OT2; OT3) which connects the output circuit to a signal line (SL). The signal line is connected with a test output circuit (Ru, Q4p, Q4n, Rd). The tristate output circuits each include a MOSFET (Q1p; Q2p; Q3p) for selectively connecting the tristate output (OT1; OT2; OT3) with a power supply terminal (Vdd) and a MOSFET (Q1n; Q2n; Q3N) for connecting the tristate output with a ground voltage level (Vss). In one test mode, a test signal is applied (i) which causes the MOSFETs (Q1p; Q2p; Q3p) to cut off forcibly cutting the current path between the power supply terminal (Vdd) and the signal line (SL) and (ii) causes the test output circuit pull-up transistor (Q4p) to close connecting a pull up resistance (Ru) between the power supply voltage level (Vdd) and the signal line (SL). In this mode, the voltage level of the signal line is set to a logic 1 or a logic 0. In this manner, the operation is equivalent to a selector for forcing the signal line to the voltage level of a logic 1 or a logic 0.Other References
| InventorAssigneeApplicationNo. 867475 filed on 04/13/1992US Classes:326/57, With field effect-transistor324/769, Field effect transistor326/16, WITH TEST FACILITATING FEATURE714/724Digital logic testingExaminersPrimary: Westin, Edward P.Assistant: Sanders, Andrew Attorney, Agent or FirmUS Patent References4608504, Interface circuit for interconnecting peripherals to an information processing deviceIssued on: 08/26/1986 Inventor: Yamamoto4866309, Multiplexed bus architecture for configuration sensing Issued on: 09/12/1989 Inventor: Bonke , et al.5136185, Local tristate control circuit Issued on: 08/04/1992 Inventor: Fleming, et al.5159273, Tri-state bus driver to support reconfigurable fault tolerant logic Issued on: 10/27/1992 Inventor: Wright, et al.5166937Arrangement for testing digital circuit devices having tri-state outputs Issued on: 11/24/1992 Inventor: Blecha, Jr. International ClassH03K 019/00Foreign Application Priority Data1991-04-24 JP |
