Semiconductor integrated tri-state circuitry with test means
Patent 5285119 Issued on February 8, 1994. Estimated Expiration Date: 
April 13, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
April 13, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesInterface circuit for interconnecting peripherals to an information processing device Multiplexed bus architecture for configuration sensing Local tristate control circuit Tri-state bus driver to support reconfigurable fault tolerant logic Arrangement for testing digital circuit devices having tri-state outputs Patent #: 5166937 InventorAssigneeApplicationNo. 867475 filed on 04/13/1992US Classes:326/57, With field effect-transistor324/769, Field effect transistor326/16, WITH TEST FACILITATING FEATURE714/724Digital logic testingExaminersPrimary: Westin, Edward P.Assistant: Sanders, Andrew Attorney, Agent or FirmInternational ClassH03K 019/00Foreign Application Priority Data1991-04-24 JPAbstractA plurality of tristate circuits (TSG1, TSG2, TSG3) each include an input circuit (NAND1, NOR1; NAND2, NOR2; NAN3, NOR3) for receiving first and second control signals ($c;goe1*, in1; $c;goe2*, in2; $c;goe3*, in3) and a tristate output circuit (Q1p, Q1n; Q2p, Q2n; Q3n). The input circuits further receiving a test signal (TEST*). The tristate circuits each include a tristate output (OT1; OT2; OT3) which connects the output circuit to a signal line (SL). The signal line is connected with a test output circuit (Ru, Q4p, Q4n, Rd). The tristate output circuits each include a MOSFET (Q1p; Q2p; Q3p) for selectively connecting the tristate output (OT1; OT2; OT3) with a power supply terminal (Vdd) and a MOSFET (Q1n; Q2n; Q3N) for connecting the tristate output with a ground voltage level (Vss). In one test mode, a test signal is applied (i) which causes the MOSFETs (Q1p; Q2p; Q3p) to cut off forcibly cutting the current path between the power supply terminal (Vdd) and the signal line (SL) and (ii) causes the test output circuit pull-up transistor (Q4p) to close connecting a pull up resistance (Ru) between the power supply voltage level (Vdd) and the signal line (SL). In this mode, the voltage level of the signal line is set to a logic 1 or a logic 0. In this manner, the operation is equivalent to a selector for forcing the signal line to the voltage level of a logic 1 or a logic 0.Other References
| |
