High electron mobility transistor
Patent 5285088 Issued on February 8, 1994. Estimated Expiration Date: 
September 16, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 16, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer Complementary field effect transistors having strained superlattice structure Field effect transistor and manufacturing method therefor Patent #: 5187379 InventorsAssigneeApplicationNo. 945500 filed on 09/16/1992US Classes:257/192, Field effect transistor257/19, Si x Ge 1-x257/194, Doping on side of heterojunction with lower carrier affinity (e.g., high electron mobility transistor (HEMT))257/200, Heterojunction formed between semiconductor materials which differ in that they belong to different periodic table groups (e.g., Ge (group IV) - GaAs (group III-V) or InP (group III-V) - CdTe (group II-VI))257/616, Containing germanium, Ge257/E21.403, With heterojunction interface channel or gate, e.g., HFET, HIGFET, SISFET, HJFET, HEMT (EPO)257/E29.247With inverted single heterostructure (i.e., with active layer formed on top of wide bandgap layer (e.g., IHEMT)) (EPO)ExaminersPrimary: Hille, RolfAssistant: Fahmy, Wael Attorney, Agent or FirmForeign Patent References
International ClassesH01L 031/072H01L 031/109 H01L 029/06 H01L 031/117 Foreign Application Priority Data1991-09-17 JPAbstractA semiconductor device capable of reducing element sizes exceedingly and a mask alignment accuracy in lithography is provided. This device has a pair of semiconductor layers for source/drain electrodes formed on the field insulating film so as to be respectively partially projected in a "overhanging-shape" over the active area. For example, using an MBE method, a selectively epitaxial growth is made with these semiconductor layers as nuclei, so that first and second semiconductor layers at the interface of which a channel is formed and a pair of semiconductor layers for source and drain electrode connections can be formed. Accordingly, the semiconductor heterojunction and gate electrode can be formed in self-alignment on the active area with the semiconductor layers pair for source/drain electrodes as the reference, so that a reduction in transistor size can be realized. It is preferable that the first semiconductor layer and second semiconductor layer making a heterojunction are made of an undoped monocrystalline SiGe layer and a monosilicon layer inverse in electroconductive polarity to the substrate, respectively. The semiconductor layers for source/drain electrode connections are preferable to have a two-level structure made of a polycrystalline SiGe layer and a polysilicon layer.Other References
Field of SearchField effect transistorDoping on side of heterojunction with lower carrier affinity (e.g., high electron mobility transistor (HEMT)) Heterojunction formed between semiconductor materials which differ in that they belong to different periodic table groups (e.g., Ge (group IV) - GaAs (group III-V) or InP (group III-V) - CdTe (group II-VI)) Between different group IV-VI or II-VI or III-V compounds other than GaAs/GaAlAs Si x Ge 1-x Field effect device With contact to source or drain region of refractory material (e.g., polysilicon, tungsten, or silicide) Containing germanium, Ge Contact of refractory or platinum group metal (e.g., molybdenum, tungsten, or titanium) Including silicide Multiple polysilicon layers | |
