Shared two level cache including apparatus for maintaining storage consistency
August 20, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesHierarchy response priority adjustment mechanism Data processing system having an intermediate buffer memory Multilevel storage system having unitary control of data transfers Cache storage line shareability control for a multiprocessor system Apparatus and method for maintaining cache memory integrity in a shared memory environment Three level memory hierarchy using write and share flags Multiprocessing system including a shared cache Cache sharing control in a multiprocessor Multi-processor system with hierarchy buffer storages Cache memory consistency control with explicit software instructions Patent #: 4713755 InventorsApplicationNo. 750430 filed on 08/20/1991US Classes:711/121Private cachesExaminersPrimary: Chan, Eddie P.Attorney, Agent or FirmForeign Patent References
International ClassesG06F 013/00G06F 012/08 AbstractA multilevel cache buffer for a multiprocessor system in which each processor has a level one cache storage unit which interfaces with a level two cache unit and main storage unit shared by all processors. The multiprocessors share the level two cache according to a priority algorithm. When data in the level two cache is updated, corresponding data in level one caches is invalidated until it is updated.Other References
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