Memory with redundant rows and columns
Address transition pulse circuit
Redundancy enable/disable circuit
Control circuit for disabling or enabling the provision of redundancy
Memory circuit having a redundant memory cell array for replacing faulty cells
Semiconductor memory system Patent #: 5107464
ApplicationNo. 910646 filed on 07/08/1992
US Classes:326/10, Redundant326/21, SIGNAL SENSITIVITY OR TRANSMISSION INTEGRITY326/106, With field-effect transistor365/200, Bad bit365/230.06Particular decoder or driver circuit
ExaminersPrimary: Westin, Edward P.
Assistant: Santamauro, Jon
Attorney, Agent or Firm
International ClassesG06F 011/16
Foreign Application Priority Data1991-07-08 JP
AbstractA redundant control circuit compares a defective address with an external address to determine whether a redundant word line is driven for a read-out operation instead of a defective word line assigned as a defective address, and keeps a redundant control signal on a precharged output signal line at an active high voltage level in the presence of the external address consistent with the defective address. A precharging unit not only charges the output signal line to the active high voltage level before arrival of the external address but also keeps the output signal line at the active high voltage level even if a current path is undesirably established from the output signal line to a discharge line in the presence of the external address consistent with the defective address, thereby preventing the defective word line from being undesirably accessed.