Extended drain self-aligned silicon gate MOSFET
Method of manufacturing a semiconductor device having conductive and insulating portions formed of a common material utilizing selective oxidation and angled ion-implantation
Method of making electrode wiring regions and impurity doped regions self-aligned therefrom
Method of fabricating polysilicon/silicon junction field effect transistors
Method of making integrated circuit with reduced narrow-width effect
Method of manufacturing a field effect transistor
Process for making a lateral bipolar transistor in a standard CSAG process
Modified four transistor EEPROM cell
Modified three transistor EEPROM cell
EEPROM memory having extended life
ApplicationNo. 915036 filed on 07/16/1992
US Classes:438/286, Asymmetric257/E21.417, With channel containing layer, e.g., p-base, fo rmed in or on drain region, e.g., DMOS transistor (EPO)257/E21.418, Vertical power DMOS transistor (EPO)257/E21.683, Simultaneous fabrication of periphery and memory cells (EPO)257/E29.009, With field relief electrode (field plate) (EPO)257/E29.152, With lateral structure (e.g., poly-silicon gate with lateral doping variation or with lateral composition variation or characterized by sidewalls being composed of conductive, resistivity) (EPO)257/E29.266, With lightly doped drain or source extension (EPO)257/E29.268, Source region and drain region having nonsymmetrical structure about gate electrode (EPO)438/289, Doping of semiconductive channel region beneath gate insulator (e.g., adjusting threshold voltage, etc.)438/297Recessed oxide formed by localized oxidation (i.e., LOCOS)
ExaminersPrimary: Hearn, Brian E.
Assistant: Nguyen, Tan T.
Attorney, Agent or Firm
Foreign Patent References
International ClassH01L 021/00
AbstractAn insulated-gate field-effect transistor (426, 452) has reduced gate oxide stress. According to one embodiment, the control gate (458) has a doped region (460) adjacent the source end of the transistor (452), and an undoped dielectric portion (462) adjacent the gate end. According to another embodiment, the drain end of the conductive gate (434) is disposed on top of a thick insulator region (432) that also acts to mitigate the high electric fields present when the transistor is subjected to a high voltage transient.