InventorAssigneeApplicationNo. 989093 filed on 12/11/1992US Classes:370/238, Least cost or minimum delay routing340/2.1, Path selection370/255, Using a particular learning algorithm or technique370/409Employing logical addressing for routing (e.g., VP or VC)ExaminersPrimary: Olms, Douglas W.Assistant: Vu, Hung Attorney, Agent or FirmInternational ClassH04J 003/26AbstractVirtual circuits are routed and grouped into virtual paths during an interactive topology design process. Virtual circuits are assigned to virtual paths that provide minimum cost to each pass through a topology design. Virtual paths are dispersed into subgroups that minimize bandwidth consumption and maximize routing flexibility. This topology optimization process is constrained to minimize use of network resources.Other References
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