Semiconductor integrated circuit having a stand-by current reducing circuit
Patent 5274601 Issued on December 28, 1993. Estimated Expiration Date: 
November 6, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
November 6, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDecoder buffer circuit incorporated in semiconductor memory device Semiconductor integrated circuit including P-channel MOS transistors having different threshold voltages Patent #: 5200921 Inventors
AssigneeApplicationNo. 972545 filed on 11/06/1992US Classes:365/230.06, Particular decoder or driver circuit327/427Field-effect transistorExaminersPrimary: LaRoche, Eugene R.Assistant: Zarabian, A. Attorney, Agent or FirmInternational ClassG11C 008/00Foreign Application Priority Data1991-11-08 JPAbstractA device parameter of a switching transistor is set in such a way that a leakage current of the switching transistor making up a power source switch which is turned off in a stand-by state is smaller than the sum total of subthreshold currents of P-channel or N-channel MOS transistors in an off state of a plurality of CMOS circuits. Therefore, the currents which flow through the plurality of CMOS circuits in the stand-by state are not determined by the subthreshold current but are determined by a small leakage current of the switching transistor. As a result, even when the CMOS circuit is shrunken and the subthreshold current increases, it is possible to reduce the current consumption in the stand-by state. | |
