Look up table implementation of fast carry for adders and counters
May 8, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProgrammable array logic circuit Conditional carry techniques for digital processors Special interconnect for configurable logic array Configurable logic element Microprocessor oriented configurable logic element Programmable logic array for carrying out logic operations of binary input signals Configurable electrical circuit having configurable logic elements and configurable interconnects Programmable logic array having feedback flip-flops connected between a product array's inputs and its outputs Programmable logic array circuit having a gate to control an output condition state of a latch thereof Patent #: 5059828 InventorsApplicationNo. 880752 filed on 05/08/1992US Classes:708/700, Binary708/672, Incrementation/decrementation708/706ParallelExaminersPrimary: Malzahn, David H.Attorney, Agent or FirmForeign Patent References
International ClassG06F 007/50AbstractLook up tables for use in programmable logic devices are modified to facilitate use of those tables to provide adders (including subtracters) and various types of counters. Each look up table is effectively partitioned into smaller look up tables when an adder or counter is required. One portion of the partitioned table is used to provide a sum out signal, while the other portion of the partitioned table is used to provide a fast carry out signal for application to the next stage of the adder or counter.Other References
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