Methods for fabricating a dual-gated semiconductor-on-insulator field effect transistor
Patent 5273921 Issued on December 28, 1993. Estimated Expiration Date: December 27, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
438/157, Plural gate electrodes (e.g., dual gate, etc.)257/E21.415, Monocrystalline silicon transistor on insulating substrate, e.g., quartz substrate (EPO)257/E29.275, With multiple gates (EPO)257/E29.277, Characterized by drain or source properties (EPO)257/E29.278, With LDD structure or extension or offset region or characterized by doping profile (EPO)257/E29.286, Monocrystalline only (EPO)438/481Utilizing epitaxial lateral overgrowth
A method for forming a dual-gated Semiconductor-On-Insulator (SOI) field effect transistor for integrated circuits includes the formation of a gate/oxide/channel/oxide/gate stack on top of an insulating layer. The process begins with the formation of a first gate electrode and first oxide layer on an insulating layer. Then, a seed hole in the insulating layer is formed exposing the underlying substrate. This is followed by the epitaxial lateral overgrowth (ELO) of monocrystalline silicon, for example, from the seed hole to on top of the first oxide layer. This monocrystalline layer forms the device channel. A second oxide and second gate electrode layer are then grown and deposited, respectively. Subsequent etch steps employing sidewall spacers are then employed to form a multilayered stack having self-aligned first and second gate electrodes. Sidewall seed holes are then used to epitaxially grow monocrystalline source and drain regions from the channel. In-situ doping can be provided to form a lightly doped source (LDS) and drain (LDD) structure with vertically displaced source and drain contacts.
Other References
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December 27, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
