Method and apparatus for substituting spare memory chip for malfunctioning memory chip with scrubbing
September 5, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesData processing system with apparatus for correcting microinstruction errors Error correction and detection systems Automatic fault recovery system for a multiple processor telecommunications switching control Method for storing data words in fault tolerant memory to recover uncorrectable errors System for periodically reading all memory locations to detect errors Reconfigurable memory using both address permutation and spare memory elements Information processing system capable of reducing invalid memory operations by detecting an error in a main memory Smart memory card architecture and interface Method and apparatus for storing digital data in off-specification dynamic random access memory devices Patent #: 5077737 InventorsApplicationNo. 755209 filed on 09/05/1991US Classes:714/7, Reconfiguration (e.g., adding a replacement storage component)714/710, Replacement of memory spare location, portion, or segment714/754Error correction during refresh cycleExaminersPrimary: Nguyen, Hiep T.Attorney, Agent or FirmForeign Patent References
International ClassG06F 011/00AbstractA computer memory maintainence apparatus tests operating system storage and identifies a malfunctioning memory chip in an on-line memory array by detecting and recording all permanent data errors using data comparison along with data complementation and substitutes a spare memory chip for the malfunctioning one for all memory read commands. All write commands are performed on both spare memory and the malfunctioning memory chip. All contents of defective chip are copied to the spare chip. The computer system maintains the scrubbing and a recording counter for each of the data bits in an ECC memory data word. The sparing logic in the memory storage system maintains the bit steering logic and controls for the spare chip. When a counter is incremented above a threshold sparing is invoked to replace the failing bit position. The system writes to the defective and spare chips in parallel even after bit steering is invoked.Other References
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