Method of fabricating an offset dual gate thin film field effect transistor
Patent 5266507 Issued on November 30, 1993. Estimated Expiration Date: 
May 18, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
May 18, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesFabrication of stacked MOS devices utilizing lateral seeding and a plurality of separate implants at different energies Semiconductor device having an improved thin film transistor Process for manufacturing stacked semiconductor devices Method of making a MOS thin film transistor with self-aligned asymmetrical structure Patent #: 5198379 InventorApplicationNo. 884773 filed on 05/18/1992US Classes:438/154, Complementary field effect transistors257/66, Field effect device in non-single crystal, or recrystallized, Semiconductor material257/903, FET CONFIGURATION ADAPTED FOR USE AS STATIC MEMORY CELL257/E21.412, Amorphous silicon or polysilicon transistor (EPO)257/E27.1, Load element being a thin film transistor (EPO)257/E29.275, With multiple gates (EPO)257/E29.279, Asymmetrical source and drain regions (EPO)438/157Plural gate electrodes (e.g., dual gate, etc.)ExaminersPrimary: Wilczewski, MaryAttorney, Agent or FirmInternational ClassesH01L 021/336H01L 021/28 H01L 029/78 AbstractA method of fabricating an offset dual gate thin film field offset transistor wherein a lower gate electrode is formed on an insulating substrate is provided. A dielectric layer deposited. A polycrystalline silicon layer deposited and patterned to overlie and extend beyond the edges of the lower gate. A dielectric layer deposited. A metal layer deposited. A photoresist layer deposited and patterned to define a upper gate electrode in the metal layer that overlies the lower gate electrode but extend beyond one edge. The exposed metal layer is removed to form the upper gate electrode. An impurity is ion implanted into the polycrystalline silicon layer to form source and drain regions, using the photoresist layer and metal layer as a mask. | |
