Method of forming a self-aligned contact utilizing a polysilicon layer
February 27, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of making single polysilicon self-aligned transistor Process for forming lightly-doped-drain (LDD) without extra masking steps Process for making BiCMOS integrated circuit having a shallow trench bipolar transistor with vertical base contacts Method of manufacturing a semiconductor device Process for forming a self-aligned contact structure Method of forming a microelectronic contact Patent #: 5114879 InventorsAssigneeApplicationNo. 842549 filed on 02/27/1992US Classes:438/586, Combined with formation of ohmic contact to semiconductor region257/E21.507, Formation of contacts to semiconductor by use of metal layers separated by insulating layers, e.g., self-aligned contacts to source/drain or emitter/base (EPO)438/595, Having sidewall structure438/637, With formation of opening (i.e., viahole) in insulative layer438/702Plural coating stepsExaminersPrimary: Maples, John S.Attorney, Agent or FirmInternational ClassH01L 021/441Foreign Application Priority Data1991-02-28 KRAbstractA method of forming a contact region having an insulating layer which is etch protected, which includes sequentially depositing a gate oxide layer 2, a first conducting layer 3 for gate electrode, a first insulating layer 4 and a second conducting layer 5 on a silicon substrate 1. A portion of the second conducting layer 5 is etched to form an etch protective layer 5A. Portions of the etch protective layer 5A, the first insulating layer 4 and the first conducting layer 3 are sequentially etched to form separated gate electrodes 3a and 3b and separated etch protective layers 5a and 5b on the gate electrodes 3a and 3b, respectively and to expose a portion of the gate oxide layer 2 to define a source region 1A. A second insulating layer 6 is deposited on the entire surface of the resulting structure. The second insulating layer 6 is etched to form a spacer 6a on each of the side walls of the gate electrodes 3a and 3b and on the first insulating layer 4 and to expose the source region 1A. A third insulating layer 7 is deposited on the entire surface of the resulting structure. A contact region 10 is formed by selectively removing the third insulating layer 7 and the gate oxide layer 2 on the source region 1A and portions of the third insulating layer 7 on the etch protective layers 5a and 5b to form a contact region having an etch protected insulating layer. | |
