Method of making a non-volatile memory cell
Patent 5264384 Issued on November 23, 1993. Estimated Expiration Date: 
August 30, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
August 30, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of making electrode wiring regions and impurity doped regions self-aligned therefrom Patent #: 4306915 InventorsAssigneeApplicationNo. 753252 filed on 08/30/1991US Classes:438/257, Having additional gate electrode surrounded by dielectric (i.e., floating gate)257/E29.307, Hot carrier produced by avalanche breakdown of PN junction (e.g., FAMOS) (EPO)438/286AsymmetricExaminersPrimary: Thomas, TomAttorney, Agent or FirmForeign Patent References
International ClassH01L 021/70AbstractIn one embodiment, a non-volatile memory cell structure 10 comprises heavily doped source 11 and drain 12 regions formed in the surface of a semiconductor substrate 8 and separated by a channel region 21. A floating gate 13 is formed over and insulated from the channel region 21 and a control gate 14 is formed over and insulated from the floating gate 13. A lightly doped region 20 is formed in the channel 21 beneath the floating gate 13 and adjoining the source region 11. The lightly doped region 20 is spaced from the surface of said substrate 8. Other embodiments and processes are also disclosed.Field of SearchWith floating gate electrode | |
