Patent ReferencesMemory error correction system System for determining status of errors in a memory subsystem Patent #: 4964130 InventorsAssigneeApplicationNo. 721959 filed on 06/27/1991US Classes:714/764, Error correct and restore714/710Replacement of memory spare location, portion, or segmentExaminersPrimary: Canney, Vincent P.Attorney, Agent or FirmInternational ClassG06F 011/10AbstractA computer system having a memory with an ECC function employs an improved method for handling corrected read data events, so transient errors caused by alpha particle hits in DRAMs may be distinguished from hard errors. When a corrected read data event occurs, a footprint defining its location is compared with previously-stored footprints to determine if this location has failed before. Also, a location showing a corrected read data event is "scrubbed" (data is read, corrected and rewritten) so transient error locations are removed. If another corrected read data event occurs for this same location, after scrubbing, then the location is assumed to have a hard fault, and so the page containing this location is replaced.Other References
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