U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Programmable logic array having local and long distance conductors

Patent 5260611 Issued on November 9, 1993. Estimated Expiration Date: Icon_subject May 8, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3473160

Programmable array logic circuit
Patent #: 4124899
Issued on: 11/07/1978
Inventor: Birkner ,   et al.

Special interconnect for configurable logic array
Patent #: 4642487
Issued on: 02/10/1987
Inventor: Carter

Logic array chip
Patent #: 4689654
Issued on: 08/25/1987
Inventor: Brockmann

Configurable logic element
Patent #: 4706216
Issued on: 11/10/1987
Inventor: Carter

User programmable integrated circuit interconnect architecture and test method
Patent #: 4758745
Issued on: 07/19/1988
Inventor: Elgamal ,   et al.

Microprocessor oriented configurable logic element
Patent #: 4758985
Issued on: 07/19/1988
Inventor: Carter

Electronically programmable gate array having programmable interconnect lines
Patent #: 4786904
Issued on: 11/22/1988
Inventor: Graham, III ,   et al.

Programmable logic device
Patent #: 4847612
Issued on: 07/11/1989
Inventor: Kaplinsky

Buffered routing element for a user programmable logic device
Patent #: 4855619
Issued on: 08/08/1989
Inventor: Hsieh ,   et al.

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Inventors

Application

No. 880942 filed on 05/08/1992

US Classes:

326/39, Array (e.g., PLA, PAL, PLD, etc.)326/41Significant integrated structure, layout, or layout interconnections

Examiners

Primary: Westin, Edward P.
Assistant: Driscoll, Benjamin D.

Attorney, Agent or Firm

Foreign Patent References

  • 1444084 GB. 07/13/1976

International Class

H03K 019/177

Abstract

A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit.

Other References

  • S. S. Yau et al., "Universal Logic Modules and Their Applications", IEEE Transactions on Computers, vol. C-19, No. 2, Feb. 1970, pp. 141-149
  • The Programmable Gate Array Data Book, Xilinx, Inc., San Jose, Calif., 1988, pp. 1-1 through 2-123
  • R. C. Minnick, "A Survey of Microcellular Research", Journal of the Association for Computing Machinery, vol. 14, No. 2, pp. 203-241, Apr. 1967
  • S. E. Wahlstrom, "Programmable Logic Arrays--Cheaper by the Millions", Electronics, Dec. 11, 1967, pp. 90-95
  • Richard G. Shoup, Programmable Cellular Logic Arrays Mar. (1970) (Ph.D. dissertation, Carnegie-Mellon University (Pittsburgh))
  • Carr et al., MOS/LSI Design and Application, Texas Instruments Electronics Series, McGraw-Hill and Co., 1972, pp. 229-258
  • F. Heutink, "Implications of Busing for Cellular Arrays", Computer Design, pp. 95-100, Nov., 1974
  • H. Fleisher et al., "An Introduction to Array Logic", IBM Journal of Research and Development, Mar. 1975, pp. 98-109
  • K. Horninger, "A High-Speed ESFI SOS Programmable Logic Array with an MNOS Version", IEEE Journal of Solid State Circuits, vol. SC-10, No. 5, Oct. 1975, pp. 331-336
  • B. Kitson et al., "Programmable Logic Chip Rivals Gate Arrays in Flexibility", Electronic Design, Dec. 8, 1983, pp. 95-101
  • Advanced Micro Devices, "The World's Most Versatile Logic Tool; AmPAL22V10", May 1984
  • Monolithic Memories, "Programmable Array Logic; PAL 20RA10", Jun. 1984
  • A. Haines, "Field-Programmable Gate Array with Non-Volatile Configuration", Microprocessors and Microsystems, vol. 13, No. 5, Jun. 1989
  • K. A. El-Ayat et al., "A CMOS Electrically Configurable Gate Array", IEEE Journal of Solid State Circuits, vol. 24, No. 3, Jun. 1989
  • F. Furtek et al., "Labyrinth: A Homogeneous Computational Medium", Proc. IEEE 1990 Custom Integrated Circuits Conference
  • H-C. Hsieh et al., "Third-Generation Architecture Boosts Speed and Density of Field-Programmable Gate Arrays", Proc. IEEE 1990 Custom Integrated Circuits Conference
  • M. Ahrens et al., "An FPGA Family Optimized for High Densities and Reduced Routing Delay", Proc. IEEE 1990 Custom Integrated Circuits Conferenc
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