U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Programmable logic element interconnections for programmable logic array integrated circuits

Patent 5260610 Issued on November 9, 1993. Estimated Expiration Date: Icon_subject September 3, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3473160

Programmable array logic circuit
Patent #: 4124899
Issued on: 11/07/1978
Inventor: Birkner ,   et al.

Semiconductor memory device
Patent #: 4398267
Issued on: 08/09/1983
Inventor: Furuyama

Special interconnect for configurable logic array
Patent #: 4642487
Issued on: 02/10/1987
Inventor: Carter

Configurable logic element
Patent #: 4706216
Issued on: 11/10/1987
Inventor: Carter

Electrically erasable programmable logic array (EEPLA)
Patent #: 4745579
Issued on: 05/17/1988
Inventor: Mead ,   et al.

User programmable integrated circuit interconnect architecture and test method
Patent #: 4758745
Issued on: 07/19/1988
Inventor: Elgamal ,   et al.

Microprocessor oriented configurable logic element
Patent #: 4758985
Issued on: 07/19/1988
Inventor: Carter

Electronically programmable gate array having programmable interconnect lines
Patent #: 4786904
Issued on: 11/22/1988
Inventor: Graham, III ,   et al.

Buffered routing element for a user programmable logic device
Patent #: 4855619
Issued on: 08/08/1989
Inventor: Hsieh ,   et al.

More ...

Inventors

Application

No. 754017 filed on 09/03/1991

US Classes:

326/41, Significant integrated structure, layout, or layout interconnections327/407Converging with plural inputs and single output

Examiners

Primary: Westin, Edward P.
Assistant: Driscoll, Benjamin D.

Attorney, Agent or Firm

Foreign Patent References

  • 1444084 GB. 07/13/1976

International Class

H03K 019/177

Abstract

A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups. Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group. Other signal conductors are provided for conveying signals between the groups. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Other References

  • R. C. Minnick, "A Survey of Microcellular Research," Journal of the Association for Computing Machinery, vol. 14, No. 2, pp. 203-241, Apr. 1967
  • Richard G. Shoup, Programmable Cellular Logic Arrays (1970) (Ph.D. dissertation, Carnegie-Mellon University (Pittsburgh))
  • F. Heutink, "Implications of Busing for Cellular Arrays," Computer Design, pp. 95-100, Nov. 1974
  • The Programmable Gate Array Data Book, Xilinx, Inc., 1991, pp. 1-3 to 1-5, 2-1 to 2-13 and 2-61 to 2-69
  • The Programmable Gate Array Data Book, Xilinx, Inc., 1988
  • M. Ahrens et al., "An FPGA family optimized for high densities and reduced routing delay", Proc. IEEE 1990 Custom Integrated Circuits Conference
  • K. A. El-Ayat et al., "A CMOS electrically configurable gate array", IEEE Journal of Solid State Circuits, vol. 24, No. 3, Jun. 1989
  • F. Furtek et al., "Labyrinth: a homogeneous computational medium", Proc. IEEE 1990 Custom Integrated circuits Conference
  • A. Haines, "Field-programmable gate array with non-volatile configuration", Microprocessors and Microsystems, vol. 13, No. 5, Jun. 1989
  • H. C. Hsieh, "Third-generation architecture boosts speed and density of field-programmable gate arrays", Proc. IEEE 1990 Custom Integrated Circuits Conference
  • S. E. Wahlstrom, "Programmable Logic Arrays-Cheaper by the Millions", Electronics, Dec. 11, 1967, pp. 90-95
  • Advanced Micro Devices, "The World's Most Versatile Logic Tool AmPAL22V10", May 1984
  • Kitson et al., "Programmable Logic Chip Rivals Gate Arrays in Flexibility", Electronic Design, Dec. 8, 1983, pp. 95-102
  • Monolithic Memories, "Programmable Array Logic PAL20RA10", Jun. 1984
  • Fleisher et al., "An Introduction to Array Logic", IBM Journal of Research and Development, Mar. 1975, pp. 98-109
  • Carr et al., MOS/LSI Design and Application, Texas Instruments Electronics Series, McGraw-Hill and Co., 1972, pp. 229-258
  • Horninger, "A High-Speed ESFI SOS Programmable Logic Array with an MNOS Version", IEEE Journal of Solid State Circuits, vol. SC-10, No. 5, Oct. 1975, pp. 331-33
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