Parallel digital processor including lateral transfer buses with interrupt switches to form bus interconnection segments
Patent 5247689 Issued on September 21, 1993. Estimated Expiration Date: 
September 21, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 21, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3141067 3226687 3226688 3226692 3750110 3815095 Bus-coupler Data processing interconnection techniques CPU-Synchronous parallel data processor apparatus CPU/Parallel processor interface with microcode extension InventorApplicationNo. 478232 filed on 02/09/1990US Classes:710/317CrossbarExaminersPrimary: Kriess, Kevin A.Attorney, Agent or FirmInternational ClassG06F 015/16AbstractA digital computer system including a large number of parallel processing modules (PPM's). Each PPM includes an arithmetic logic unit (ALU), an instruction decoder, and internal bus switching. The main memory is organized in columns and rows with a separate column for each PPM port. Each PPM preferably includes at least three ports to permit parallel transfer of instructions and data to the PPM's. The ports of the PPM's are also connected to segmented lateral transfer buses which operate in conjunction with the internal bus switching of the PPM's to permit tandem ALU operation. | |
