U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Method to getter contamination in semiconductor devices

Patent 5244819 Issued on September 14, 1993. Estimated Expiration Date: Icon_subject October 22, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3909307

3923567

3929529

Method of ion implantation through an electrically insulative material
Patent #: 3945856
Issued on: 03/23/1976
Inventor: Koenig ,   et al.

Method of gettering using backside polycrystalline silicon
Patent #: 4053335
Issued on: 10/11/1977
Inventor: Hu

Gettering semiconductor wafers with a high energy laser beam
Patent #: 4131487
Issued on: 12/26/1978
Inventor: Pearce ,   et al.

High performance silicon wafer and fabrication process
Patent #: 4144099
Issued on: 03/13/1979
Inventor: Edmonds ,   et al.

Method of providing gettering sites through electrode windows
Patent #: 4371403
Issued on: 02/01/1983
Inventor: Ikubo ,   et al.

Wafer fabrication by implanting through protective layer
Patent #: 4498227
Issued on: 02/12/1985
Inventor: Howell ,   et al.

Process of gettering semiconductor devices
Patent #: 4561171
Issued on: 12/31/1985
Inventor: Schlosser

More ...

Inventor

Assignee

Application

No. 781711 filed on 10/22/1991

US Classes:

438/402, And gettering of substrate257/E21.32, Of silicon on insulator (SOI) (EPO)257/E21.563, Using silicon implanted buried insulating layers, e.g., oxide layers, i.e., SIMOX technique (EPO)438/474, Ionized radiation (e.g., corpuscular or plasma treatment, etc.)438/476By layers which are coated, contacted, or diffused

Examiners

Primary: Hearn, Brian E.
Assistant: Holtzman, Laura M.

Attorney, Agent or Firm

International Class

H01L 021/308

Abstract

A frontside gettering method for removing metallic contamination from a thin film SOI or SOS silicon device. Damage sites are created by ion implantation into inactive regions of a silicon substrate. An annealing step causes metallic contamination to diffuse from the active device region to the inactive region. The inactive region material is removed prior to subsequent processing steps.

Other References

  • Wolf, Silicon Processing for the VLSI Era, vol. 2, Lattice Press, Sunset Beach, 1990 pp. 72-7
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