Patent ReferencesSwitching node for switching data signals transmitted in data packets Switching node for switching data signals transmitted in data packets Method and apparatus for input-buffered asynchronous transfer mode switching Dual port memory buffers and a time slot scheduler for an ATM space division switching system Technique for resolving output port contention in a high speed packet switch Patent #: 5157654 InventorsAssigneeApplicationNo. 770214 filed on 10/03/1991US Classes:370/398, Centralized switching370/416, Contention resolution for output370/427Space switchingExaminersPrimary: Safourek, Benedict V.Assistant: Kizou, H. Attorney, Agent or FirmInternational ClassH04L 012/56AbstractBroadband ATM switches for switching ATM packetized data in timeslots are disclosed. In one embodiment, the switch includes input buffer, a space switch for connecting input ports and output ports at successive timeslots and a system scheduler. The timeslot utilization processing is carried out by using a content addressable memory. A bit map is provided for registering the timeslot utilization of the input ports and the output ports. An encoder determines the earliest commonly available timeslot for connecting input ports and their requested output ports. There is further disclosed an architecture in which groups of input ports share common buffer memories and in which the system scheduler processes grouped inputs, thus taking advantage of the architecture's similar characteristics and advantages to those of the common memory switch.Other References
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