U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Broadband input buffered ATM switch

Patent 5241536 Issued on August 31, 1993. Estimated Expiration Date: Icon_subject October 3, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Switching node for switching data signals transmitted in data packets
Patent #: 4922488
Issued on: 05/01/1990
Inventor: Niestegge

Switching node for switching data signals transmitted in data packets
Patent #: 4947387
Issued on: 08/07/1990
Inventor: Knorpp, deceased, et al.

Method and apparatus for input-buffered asynchronous transfer mode switching
Patent #: 5126999
Issued on: 06/30/1992
Inventor: Munter, et al.

Dual port memory buffers and a time slot scheduler for an ATM space division switching system
Patent #: 5130975
Issued on: 07/14/1992
Inventor: Akata

Technique for resolving output port contention in a high speed packet switch Patent #: 5157654
Issued on: 10/20/1992
Inventor: Cisneros

Inventors

Assignee

Application

No. 770214 filed on 10/03/1991

US Classes:

370/398, Centralized switching370/416, Contention resolution for output370/427Space switching

Examiners

Primary: Safourek, Benedict V.
Assistant: Kizou, H.

Attorney, Agent or Firm

International Class

H04L 012/56

Abstract

Broadband ATM switches for switching ATM packetized data in timeslots are disclosed. In one embodiment, the switch includes input buffer, a space switch for connecting input ports and output ports at successive timeslots and a system scheduler. The timeslot utilization processing is carried out by using a content addressable memory. A bit map is provided for registering the timeslot utilization of the input ports and the output ports. An encoder determines the earliest commonly available timeslot for connecting input ports and their requested output ports. There is further disclosed an architecture in which groups of input ports share common buffer memories and in which the system scheduler processes grouped inputs, thus taking advantage of the architecture's similar characteristics and advantages to those of the common memory switch.

Other References

  • "Network, Transport and Switching Integration for Broadband Communications" by J. Y. Hui, IEEE Network, Mar. 89, pp. 40-51
  • "Input Versus Output Queueing on a Space-Division Packet Switch" by M. J. Karol et al, IEEE Transactions on Communications, vol. COM-35, No. 12, Dec. 87, pp. 1347-1356
  • "Large-Scale ATM Multi-stage Switching Network with Shared Buffer Memory Switches" by Y. Sakurai et al, IEEE Communications Magazine, Jan. 91, pp. 90-9
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