Method of manufacturing semiconductor device having interconnection layer contacting source/drain regions
August 6, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProcess for forming TiSi2 layers of differing thicknesses in a single integrated circuit Method for the self-aligned silicide formation in IC fabrication Method to reduce silicon area for via formation Submicron lightly doped field effect transistors Method of producing layer structure of a memory cell for a dynamic random access memory device Method of making a stacked capacitor DRAM cell Semiconductor memory device with pillar-shaped insulating film Method of making dram cell with stacked capacitor Patent #: 5061651 InventorsApplicationNo. 925148 filed on 08/06/1992US Classes:438/253, Stacked capacitor257/E21.654, Characterized by type of transistor; manufacturing of transistor (EPO)257/E23.019, Consisting of layered constructions comprising conductive layers and insulating layers, e.g., planar contacts (EPO)257/E27.089Storage electrode having multiple wings (EPO)ExaminersPrimary: Thomas, TomAttorney, Agent or FirmForeign Patent References
International ClassH01L 021/70Foreign Application Priority Data1990-05-02 JPAbstractA semiconductor device includes a MOS type field effect transistor whose gate electrode (4) has its surface covered with a first insulating film (5) and left and right sides provided with a pair of second insulating films (10). A first conductive layer (12, 13) is formed on the surface of the source/drain region (8, 11) and the surface of one of a pair of second insulating films (10) which are positioned on one side of the gate electrode (4). A third insulating film (24b) is formed at least on the surface of the second insulating film (10) on which the first conductive layer (12, 13) is not formed. A second conductive layer (18) is provided on the surface of the third insulating film (24b) and on the source/drain region (8, 11) on which the third insulating film (24b) is formed. This structure enables provision of a semiconductor device in which a contact hole can be formed in self-alignment, independent from the influence of errors in the step of patterning a resist mask.Other References
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