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Overmolded semiconductor device having solder ball and edge lead connective structure

Patent 5239198 Issued on August 24, 1993. Estimated Expiration Date: Icon_subject July 2, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Flat package for integrated circuit devices
Patent #: 4264917
Issued on: 04/28/1981
Inventor: Ugon

Compliant lead clip
Patent #: 4647126
Issued on: 03/03/1987
Inventor: Sobota, Jr.

Semiconductor device having stacking structure
Patent #: 4807021
Issued on: 02/21/1989
Inventor: Okumura

Baseboard for orthogonal chip mount
Patent #: 4922378
Issued on: 05/01/1990
Inventor: Malhi, et al.

Gull-wing zig-zag inline lead package having end-of-package anchoring pins
Patent #: 4967262
Issued on: 10/30/1990
Inventor: Farnsworth

Edge-mounted, surface-mount package for semiconductor integrated circuit devices
Patent #: 4975763
Issued on: 12/04/1990
Inventor: Baudouin, et al.

Thin, molded, surface mount electronic device
Patent #: 5018005
Issued on: 05/21/1991
Inventor: Lin, et al.

Semiconductor package and computer using the package Patent #: 5095359
Issued on: 03/10/1992
Inventor: Tanaka, et al.

Inventors

Assignee

Application

No. 907970 filed on 07/02/1992

US Classes:

257/693, External connection to housing257/691, Having power distribution means (e.g., bus structure)257/779, Solder wettable contact, lead, or bond257/787, ENCAPSULATED257/E21.502, Encapsulation, e.g., encapsulation layer, coating (EPO)257/E23.064For flat cards, e.g., credit cards (EPO)

Examiners

Primary: Hille, Rolf
Assistant: Clark, S. V.

Attorney, Agent or Firm

International Classes

H01L 023/12
H01L 023/14
H01L 023/48

Foreign Application Priority Data

1989-09-06 JP

Abstract

A low cost manufacturing method is used to fabricate a small multiple chip semiconductor device (10). In one embodiment, a first pattern of conductive traces (14) is formed on one surface of a substrate (12), and a second pattern of traces (16) is formed on a second surface of the substrate (12). A first semiconductor die (20) is interconnected to the first traces (14), and a package body (24) is formed around the first die and a portion of the traces. A second semiconductor die (26) is interconnected to the second traces (16) on the second surface. A second package body (28) is formed around the second die and a portion of the traces (16). Solder balls (32) are coupled to exposed portions of the second traces (16) around the perimeter of the package body (28) to establish external power and ground connections to each die. Edge leads (36) are externally soldered to the traces (14 & 16) around the periphery of the substrate (12) to establish remaining electrical connections.

Other References

  • "Clipped Decoupled Twin-Carrier Module for IC Memory Chips"-IBM Technical Disclosure Bulletin-Hinrichsmeyer et al vol. 27, No. 8, Jan. 198
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