U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Receiver distortion correction circuit and method

Patent 5237332 Issued on August 17, 1993. Estimated Expiration Date: Icon_subject February 25, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3845484

Distortion measurement system
Patent #: 4340854
Issued on: 07/20/1982
Inventor: Jones ,   et al.

Disciplined oscillator system with frequency control and accumulated time control
Patent #: 4525685
Issued on: 06/25/1985
Inventor: Hesselberth ,   et al.

Coherent receiver phase and amplitude alignment circuit
Patent #: 4584710
Issued on: 04/22/1986
Inventor: Hansen

Adaptive predistortion circuit
Patent #: 4967164
Issued on: 10/30/1990
Inventor: Sari

Transmitter phase and amplitude correction for linear FM systems
Patent #: 4968968
Issued on: 11/06/1990
Inventor: Taylor

Midlevel carrier modulation and demodulation techniques
Patent #: 4989219
Issued on: 01/29/1991
Inventor: Gerdes, et al.

Linearized differential amplifier
Patent #: 5079515
Issued on: 01/07/1992
Inventor: Tanimoto

Frequency feedback linearizer Patent #: 5172123
Issued on: 12/15/1992
Inventor: Johnson

Inventors

Application

No. 841142 filed on 02/25/1992

US Classes:

342/174, Calibrating330/259, Having D.C. feedback bias control for stabilization330/290, Including D.C. feedback bias control for stabilization342/91, Gain or threshold455/205, Frequency or phase modulation455/305With balancing or neutralizing

Examiners

Primary: Sotomayor, John B.

Attorney, Agent or Firm

International Classes

G01S 007/40
H04B 001/10
H04B 001/12

Abstract

A distortion correction circuit having a mechanism for intercepting a distorted output signal from a receiver and for generating an Nth order signal. A circuit is provided to subtract the Nth order signal from the distorted output signal for providing a circuit output signal. Finally, a feedback loop is provided to feed back the circuit output signal for controlling the Nth order signal and for providing a distortion corrected circuit output signal. In a preferred embodiment, the distortion correction circuit includes a calibration circuit which provides a calibration signal employed to linearize a receiver channel. The receiver channel includes a plurality of receiver stages which receive the calibration signal and provide the distorted output signal which is intercepted and directed to a cubing circuit. The cubing circuit generates an error correction signal controlled by the feedback loop to cancel the distortion component of the distorted output signal. In the preferred embodiment, the feedback loop controls the amplitude and phase of the error correction signal while in another illustrative embodiment, only the amplitude of the error correction signal is controlled.Thus, the invention discloses a correction circuit arrangement for a receiver channel which provides a distortion corrected output signal by effectively removing the distortion generated by the receiver.

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