Dynamic random access memory cell having a stacked-trench capacitor that is resistant to alpha particle generated soft errors, and method of manufacturing same
Patent 5234856 Issued on August 10, 1993. Estimated Expiration Date: 
April 15, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
April 15, 2012. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor memory device with stacked capacitor structure and the manufacturing method thereof Method for making an electrically erasable programmable read only memory cell having a three dimensional floating gate Method of making a DRAM cell with stacked trench capacitor Patent #: 5066608 InventorApplicationNo. 869683 filed on 04/15/1992US Classes:438/244, Utilizing stacked capacitor structure (e.g., stacked trench, buried stacked capacitor, etc.)257/E21.648, Capacitor stacked over transfer transis tor (EPO)257/E21.651, Capacitor in U- or V-shaped trench in substrate (EPO)257/E27.094Having storage electrode extension stacked over the transistor (EPO)ExaminersPrimary: Chaudhuri, OlikAssistant: Trinh, Loc Q. Attorney, Agent or FirmInternational ClassesH01L 021/44H01L 021/70 AbstractA new stacked-trench DRAM cell has a trench that is self-aligned to an adjacent field oxide region and the dielectric spacer insulated edge of the access transistor gate. The trench is lined with dielectric material and an arsenic-doped polysilicon storage node plate makes contact with the storage node junction on a horizontal surface on the lip of the trench. The horizontal surface is exposed following trench formation by etching away an outer portion of the transistor gate spacer, which is comprised of a material that is selectively etchable with respect to an inner portion of the spacer. Since the contact area between the storage node plate and the storage node junction is limited to this very small area, the potential for leakage of capacitor charge into the substrate is minimized.Field of SearchCapacitor in trenchVertical transistor Inversion layer capacitor With floating gate electrode Parallel interleaved capacitor electrode pairs (e.g., interdigitized) Voltage variable capacitor (i. e., capacitance varies with applied voltage) With capacitor electrodes connection portion located centrally thereof (e.g., fin electrodes with central post) With means to insulate adjacent storage nodes (e.g., channel stops or field oxide) Storage node isolated by dielectric from semiconductor substrate Stacked capacitor With additional contacted control electrode Variable threshold (e.g., floating gate memory device) Storage Node isolated by dielectric from semiconductor substrate With increased effective electrode surface area (e.g., tortuous path, corrugated, or textured electrodes) Stacked capacitor With high dielectric constant insulator (e.g., Ta 2 O 5 ) | |
