Patent References 3562710 Instruments and methods for measuring characteristics of only a selected portion of a transmission channel 4091240 Phase delay simulator Test equipment for a teletex television receiver Method of and system for evaluating bit errors in testing a signal path BPSK synchronizer using computational analysis Method and apparatus for testing remote communication systems Establishment of bit synchronization in a data transmitting/receiving system Satellite delay simulation system InventorsAssigneeApplicationNo. 706806 filed on 05/29/1991US Classes:375/224, TESTING703/13SIMULATING ELECTRONIC DEVICE OR ELECTRICAL SYSTEMExaminersPrimary: Kuntz, CurtisAssistant: Ghebretinsae, T. Attorney, Agent or FirmInternational ClassesH04B 017/00G06F 011/00 AbstractA communications stimulation system allows a user to perform a quantitative or subjective test of digital baseband devices over wireless channels using actual measured or modeled propagation data. The digital wireless communication simulation system is capable of simulating the transient nature of channels and radio hardware so that loss of synchronization can be included in the simulation. The simulator is a combination of computer software and hardware that computes a convolution, in the time domain, of a sequence of binary digits or data symbols (i.e., the data stream) with a computer model of a radio transmitter, a propagation channel or channels and a receiver. The transmitter typically comprises a coder, a pulse shaper, a modulator, and a spreader. The propagation channel or channels may include impulsive and average noise levels, co-channel interference and adjacent interference levels, fading and multipath propagation events, and non-linear channel and radio system effects. The receiver system typically comprises at least a filter bank, a demodulator, a despreader, a synchronizer, a detector, and a decoder. The data stream may either be random or applied by the user. The software computes the bit-by-bit sequence for replay at a later time. Once stored, the bit-by-bit error sequence can be clocked through a hardware data port and compared with an applied data stream in real time. The output of the hardware data port is a real time sequence of bits that has errors due to the bit-by-bit simulation computed earlier by the software.Other References
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