Processor scheduling method for iterative loops
Patent 5230053 Issued on July 20, 1993. Estimated Expiration Date: 
February 5, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
February 5, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesParser-based attribute analysis Method for converting a source program having a loop including a control statement into an object program Compiling method for vectorizing multiple do-loops in source program Compiling a source program by analyzing a subscript of an array included in a loop processing of a computer Signal transmission performance evaluation device in an optical communication apparatus Patent #: 5267068 InventorAssigneeApplicationNo. 650819 filed on 02/05/1991US Classes:717/150, Loop compiling717/156, Using flow graph717/161Including scheduling instructionsExaminersPrimary: Heckler, Thomas M.Attorney, Agent or FirmInternational ClassG06F 009/06Foreign Application Priority Data1990-02-05 JPAbstractA compiling method is described whereby a source program written in a conventional high-language for execution by a serial architecture computer can be automatically converted to an object program for parallel execution by a multi-processor computer, without intervention by a programmer. Single loops or nested loops in source program are detected, and where possible are coded for concurrent execution of the outermost loop, with loop interchange in a nested loop, or fission of a loop into a plurality of adjacent loops being performed if necessary to enable concurrentization.Other References
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