High density semiconductor memory module using split finger lead frame
July 17, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesElectronic device package having solder leads and methods of assembling the package Integrated circuit package Dual electronic component assembly Stacked interdigitated lead frame assembly Integrated circuit package having interconnected leads adjacent the package ends Component module for piggyback mounting on a circuit package having dual-in-line leads Packaging system for multiple semiconductor devices Lead frame for semi-conductor device and process of connecting same Semiconductor package with high density I/O lead connection Package semiconductor chip InventorsApplicationNo. 554635 filed on 07/17/1990US Classes:365/63, INTERCONNECTION ARRANGEMENTS257/666, LEAD FRAME257/670, With separate tie bar element or plural tie bars257/676, With structure for mounting semiconductor chip to lead frame (e.g., configuration of die bonding flag, absence of a die bonding flag, recess for LED)257/E23.039, Chip-on-leads or leads-on-chip techniques, i.e., inner lead fingers being used as die pad (EPO)257/E23.047, Characterized by bent parts (EPO)257/E23.048, Bent parts being outer leads (EPO)257/E23.052, Assembly of semiconductor devices on lead frame (EPO)257/E23.068, Additional leads joined to metallizations on insulating substrate, e.g., pins, bumps, wires, flat leads (EPO)361/813Lead frameExaminersPrimary: Dixon, Joseph L.Assistant: Whitfield, Michael A. Attorney, Agent or FirmForeign Patent References
International ClassesG11C 005/06H01L 023/495 H01L 023/50 H05K 005/02 Foreign Application Priority Data1989-07-18 EPAbstractThe semiconductor memory module comprises a housing of plastic or ceramic in which two chips are stacked together back-to-back. The pads of the chips are electrically connected by wire bonding to beam leads which comprise outer bond leads, generally arranged outside the housing to form the contact pins or contact leads of the module to a printed circuit board, and inner bond leads in the housing. The inner bond leads are split and spread in the area of the inner lead bond ends into upper and lower sets forming a gap for receiving and holding the stacked chips.Field of SearchFORMAT OR DISPOSITION OF ELEMENTSHARDWARE FOR STORAGE ELEMENTS INTERCONNECTION ARRANGEMENTS LEAD FRAME With separate tie bar element or plural tie bars Small lead frame (e.g., "spider" frame) for connecting a large lead frame to a semiconductor chip With structure for mounting semiconductor chip to lead frame (e.g., configuration of die bonding flag, absence of a die bonding flag, recess for LED) | |
