Programmable controller processor with an intelligent functional module interface
October 30, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesProgrammable logic controller Programmable controller for using coded I/O data technique Programmable controller for executing block transfer with remote I/O interface racks Interface control system for high speed processing based on comparison of sampled data values to expected values Single bit storage and retrieval with transition intelligence Method and apparatus for exchanging multiple data bytes with an I/O module in a single scan. Programmable controller with I/O expansion module located in one of I/O module positions for communication with outside I/O modules Multiple processor communications system Method and apparatus for linking processors in a hierarchical control system Microprogrammable asynchronous controllers for digital electronic systems InventorsAssigneeApplicationNo. 605891 filed on 10/30/1990US Classes:700/11, Sequential or selective710/1INPUT/OUTPUT DATA PROCESSINGExaminersPrimary: Ruggiero, JosephAttorney, Agent or FirmForeign Patent References
International ClassesG06F 009/06G06F 013/10 AbstractA programmable controller has a rack that houses and electrically connects a number of I/O modules and a processor module. The processor module includes a external communication network interface, a system memory, a processor section which executes a user-defined control program and a I/O interface that handles the exchange of data with the other modules. The I/O interface has circuitry for pre-processing data from defined input modules, thereby relieving the processing section of certain tasks. The shared memory contains information defining the input module from which to obtain data for pre-processing and the bits of that data to be examined for specified logic level transitions. The stored information also designates the frequency at which the data is to be read from the defined input module and how many occurrences of the specified logic level transitions must take place before the I/O interface signals the processor section that the pre-processing is complete. | |
