Abstract

A data processing system includes an internal cache memory in a secure physical region that is not accessible to a user of the system. An external memory is positioned outside of the secure physical region and stores encrypted and non-encrypted (i.e., plaintext) data and instructions. An instruction enables access of a private key contained within the secure physical region which is used to decrypt an encrypted master key that accompanies encrypted data and instructions. An interface circuit in the secure physical region decrypts each encrypted master key through the use of the private key and also decrypts encrypted data and instructions associated with each decrypted master key. A central processor accesses segments of both non-encrypted and encrypted data and instructions from the external memory and causes the interface circuit to employ a decrypted master key to decrypt data and instructions and to store the decrypted information in the internal memory cache. Non-encrypted data and instructions are directly stored in the internal memory cache.