Methodology for deriving executable low-level structural descriptions and valid physical implementations of circuits and systems from high-level semantic specifications and descriptions thereof
Patent 5222030 Issued on June 22, 1993. Estimated Expiration Date: 
June 22, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 22, 2010. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References T940008 Hardware logic simulator Logic Synthesizer Method for physical VLSI-chip design Integrated circuits with component placement by rectilinear partitioning Knowledge based method and apparatus for designing integrated circuits using functional specifications Synthetic netlist system and method Patent #: 4967367 InventorsAssigneeApplicationNo. 507201 filed on 04/06/1990US Classes:716/11, Layout editor (e.g., updating)703/15, Including logic716/6, Timing analysis (e.g., delay time, path delay, latch timing)716/18Logical circuit synthesizerExaminersPrimary: Trans, Vincent N.Attorney, Agent or FirmInternational ClassG06F 015/60AbstractA methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure. The methodology includes using estimators, based on data gathered over a number of realized designs, for partitioning and evaluating a design prior to logic synthesis. From the structural description, a physical implementation of the device is readily realized.Other References
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