Electrically alterable non-volatile memory with n-bits per memory cell
February 8, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod and device for the storage of analog signals Charge coupled device memory with method of doubled storage capacity and independent of process parameters and temperature Acquisition and storage of analog signals ROM memory cell with 2n FET channel widths ROM Storage location having more than two states Multiple bit read-only memory cell and its sense amplifier Multi-level charge-coupled device memory system including analog-to-digital and trigger comparator circuits Read-only storage using enhancement-mode, depletion-mode or omitted gate field-effect transistors Memory with reference voltage generator Multi-bit read only memory circuit InventorApplicationNo. 652878 filed on 02/08/1991US Classes:365/185.21, Sensing circuitry (e.g., current mirror)365/45, ANALOG STORAGE SYSTEMS365/185.19, Multiple pulses (e.g., ramp)365/185.2, Reference signal (e.g., dummy cell)365/185.22, Verify signal365/185.29, Erase365/186Single device per bitExaminersPrimary: Fears, Terrell W.International ClassG11C 013/00AbstractThe bit storage density of an Electrically Alterable Non-Volatile Memory (EANVM) cell is improved by increasing the number of bits that are stored on an individual memory cell, without increasing the size and complexity of the memory cell, by allowing a non-volatile memory cell to assume 2 n discrete memory states. A multi-bit memory cell uses a floating gate FET which is electrically programmed to 2 n different thresholds. The 2 n different conductivity states of the FET are provided as information storage states for the cell.Other References
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