U.S. patents available from 1976 to present.
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Current mode logic circuits employing IGFETS

Patent 5216295 Issued on June 1, 1993. Estimated Expiration Date: Icon_subject August 30, 2011. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Current mode logic switching circuit having a Schmitt trigger
Patent #: 4812676
Issued on: 03/14/1989
Inventor: Yang ,   et al.

Bidirectional semiconductor device having only one one-directional device
Patent #: 4825098
Issued on: 04/25/1989
Inventor: Aoyama

Semiconductor integrated circuit Patent #: 4858191
Issued on: 08/15/1989
Inventor: Higuchi ,   et al.

Inventor

Assignee

Application

No. 753444 filed on 08/30/1991

US Classes:

326/115, Source-coupled logic (e.g., current mode logic (CML), differential current switch logic (DCSL), etc.)326/48, Bipolar transistor326/83, Field-effect transistor327/203, Including field-effect transistor327/212With clock input

Examiners

Primary: Dzierzynski, Paul M.
Assistant: Ratliff, R. A.

Attorney, Agent or Firm

International Class

H03K 019/094

Abstract

Counting and division circuits include an input differential stage connected to a cross-coupled differential stage. The input stage includes first and second IGFETS whose gate electrodes are respectively connected to first and second inputs, whose drains are respectively connected to first and second outputs, and whose sources are connected to the drain of a third IGFET whose source is grounded. The cross-coupled stage includes fourth and fifth IGFETs which are cross-coupled in that the gate of the fourth IGFET and the drain of the fifth IGFET are directly connected to the first output and the gate of the fifth IGFET and the drain of the fourth IGFET are directly connected to the second output. The sources of the fourth and fifth IGFETs are connected in common to the drain of a sixth IGFET whose source is grounded. Control signals are applied to the gates of the third and sixth IGFETS for selectively and alternately turning them on one at a time and, simultaneously, setting the level of the current flowing through the differentially connected IGFETS in their drain circuit.

Other References

  • Heimsch et al.; Merged CMOS/Bipolar Current Switch Logic(MCSL); Journal of Solid State Circuits, vol. 24, No. 5, Oct., 1989; p. 1307
  • Hong-Ih Cong et al.; Multigigahertz CMOS Dual-Modulus Prescalar IC: Journal of Solid State Circuits, vol. 23, No. 5, Oct., 1988; p. 118
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