Non-volatile semiconductor memory
Method of fabricating field-effect transistor utilizing improved gate sidewall spacers
Electrically programmable memory device employing source side injection
EEPROM cell with integral select transistor
EPROM device using asymmetrical transistor characteristics Patent #: 4852062
ApplicationNo. 694674 filed on 05/02/1991
US Classes:438/257, Having additional gate electrode surrounded by dielectric (i.e., floating gate)257/E21.422, With floating gate (EPO)438/261Multiple interelectrode dielectrics or nonsilicon compound gate insulator
ExaminersPrimary: Hearn, Brian E.
Assistant: Chaudhari, C.
Attorney, Agent or Firm
Foreign Patent References
International ClassH01L 021/266
Foreign Application Priority Data1990-05-09 JP
AbstractA method of manufacturing a floating gate type nonvolatile memory cell having an offset region, wherein the length of the offset region is defined by the portion of the substrate covered by the injection blocking film formed on the side wall of the floating gate electrode. Thus, the offset region is self-aligned with respect to the side wall of the floating gate electrode. Moreover, since the insulating film formed on the floating gate electrode includes a nitride film, it is damaged little while the injection blocking film is being formed on or removed from the side wall of the floating gate electrode. In addition, when an oxide film is formed on the offset region, substantially no additional oxide film is formed on the nitride film in the insulating film on the floating gate electrode, and the thickness of the insulating film does not change.